1. Field of the Invention
The present invention relates to a flat panel display apparatus, and more particularly to a flat panel display apparatus having an on-screen display (OSD) function.
2. Description of the Related Art
Display units of an analog system use an on-screen display driver appropriately designed to meet the characteristics of such display units. For instance, in the case of cathode ray tube monitors (CRT's), an appropriate OSD driver is used which is designed to include a phase locked loop (PLL) circuit adapted to generate an independent clock signal to be used as a clock for an operation of the OSD driver.
Meanwhile, where such an OSD driver, which is mainly adapted for monitors of an analog system, is used for flat panel display units, various problems are encountered. For example, although the OSD driver internally generates an independent clock signal to be used as a clock for an operation thereof, this clock is not necessarily synchronized with a system clock from a flat panel display unit to which the OSD driver is applied. In this case, undesirable noise is generated.
U.S. Pat. No. 4,492,979 entitled Synchronizing Circuit for Matrix Television Set to Ikeda discloses a synchronizing circuit suitable for a matrix television set using a flat display, such as comprised of liquid crystals, light emitting diodes or electro-luminescent elements in place of a cathode ray tube. It is disclosed that signals necessary for horizontal and vertical scanning, or the like, are obtained by dividing the signal from an oscillator circuit, wherein the frequency of the oscillator circuit does not equal that of the horizontal scanning signal, that is, in the order of 16 KHz. It is further disclosed phase comparison is performed on a horizontal synchronizing signal and a scanning signal, which is obtained by dividing the signal from the oscillator circuit, to apply negative feedback to the oscillator circuit whereby synchronization is performed.
U.S. Pat. No. 4,962,427 entitled TV Receiver Including Multistandard OSD to Lunn, et al. discloses a television receiver including a MPU and OSD circuitry on a single chip, wherein the OSD circuitry includes multisystem detection circuitry which counts the number of horizontal lines between vertical flyback pulses to determine the vertical frequency of the received standard signal and measures the time of a horizontal line using a fixed frequency signal to determine the horizontal frequency of the received standard signal and uses this information to control the outputs of a PLL to synchronize the receiver to the received standard. It is disclosed the PLL includes a VCO having a constant offset current applied to the control terminal to prevent alternating phases of the output control signal from the loop phase detector, which alternating phases cause jitter in the display.
U.S. Pat. No. 4,998,169 entitled Flat-panel Display Unit for Displaying Image Data from Personal Computer or the like to Yoshioka, discloses a flat-panel display unit including a basic clock pulse generator which produces a basic clock pulse having an oscillation frequency equal to an integer multiple of a dot clock-pulse frequency of the image data signal. The flat-panel display unit also includes a horizontal synchronizing signal detector which converts an input horizontal synchronizing signal to a pulse synchronous with the basic clock pulse, and a dot clock pulse generator which divides the basic clock pulse into clock pulses having a period equal to the dot clock pulses of the image data signal using an output of the horizontal synchronizing signal detector as a synchronous reset signal.
U.S. Pat. No. 5,303,048 entitled Circuit for Synchronizing an On-screen Display (OSD) on a Picture Screen to Chiok, discloses in a television receiver, a source of super sandcastle pulse is connected via a horizontal sync signal extracting first circuit and the vertical sync signal extracting second circuit to the horizontal and vertical sync input terminals of an OSD processor. It is disclosed that such a super sandcastle pulse provides good and stable relationship between H and V so that flicker and jitter on the screen during OSD do not occur.
U.S. Pat. No. 5,774,189 entitled An Screen Display to Ishii, discloses the OSD as including a plurality of holding circuits for outputting to a mixing circuit pixel data for characters or patterns synchronously with a horizontal synchronization signal, wherein the pixel data for the characters or patterns to be displayed are supplied to the holding circuits by a memory through a plurality of channels, the number of which is equal to the number of the holding circuits, so that a display signal for displaying the pixel data in a plurality of display areas is generated by the mixing circuit.
U.S. Pat. No. 5,796,392 entitled Method and Apparatus for Clock Recovery IN a Digital Display Unit to Eglit, discloses a clock recovery circuit in a digital display unit for recovering a time reference signal associated with analog display data. The clock recovery circuit is disclosed as including a phase-locked loop (PLL) implemented in digital domain and an analog filter to eliminate any undesirable frequencies from the output signal of the PLL. The PLL is disclosed as including independent control loops to track long term frequency drifts of the time reference signal and the transient phase differences respectively. It is disclosed by providing such independent control loops, the generated clock can be better synchronized with the time reference signal.